In the current state of integrated circuit technology, an integrated circuit device will often be in the form of a die. Such a die will typically be mounted onto an underlying substrate such as a carrier substrate to form a “package.” For example, some packages will include one or more dies coupled to a substrate such as a leadframe, which is frequently made of copper or copper alloy material, and may include a die paddle to support the die.
Interconnecting a die with a leadframe sometimes involves wire bonding. For example, for a quad flat package, bond pads of a die may be wire-bonded on all four sides and the wires may then extend outward from the die to the bond fingers around the periphery of the leadframe.
In multichip packages, wire bonding from those sides of a die that abut another die may be problematic. Long wires are sometimes used to “hurdle” an intermediate die (that is, a die lying between a bond finger and the die to which interconnection is being made). Long wires may result in shorting if wires were to touch during subsequent operations (e.g., during encapsulation). Even if shorting were avoided, long wires may still be undesirable due to increased signal transmission time.
Certain efforts have been made to remedy these problems. For example, micro-printed circuit boards (PCB) are sometimes placed underneath one or more dies to provide an interconnection pathway. In these situations, a die may be coupled to the PCB and the other side of the PCB may be coupled to a bond finger. Unfortunately, this process is expensive, complex, and time-consuming. Sometimes, multichip packages are forgone altogether, and single-chip packages are used instead. This “solution,” however, simply adds cost, in terms of time and money, to packaging operations.